/diy/ - Do It Yourself

>>1433952
d'oh, 2 was supposed to apply to 1 and also the oscillator power. you could have routed U3 power etc. from the board edge VCC, on the other side of the output pin, and saved two vias (inductors)
as for 1, it's a bit silly starting a trace on the top and switching sides right away
>opposite order
hence the suggestion to just build a big bundle near the horizontal center of the board and then sort it out at the connector end. otoh I usually just change up my connector pinouts to match easy board routing, where possible. also SRAM doesn't care which order address or data lines are in, you could have flowed thru the IC and put your ground plane perturbations nearer the edge of the board, out of current paths. but be careful between SOIC pins. make sure the board house has soldermask registration/resolution sufficient to cover traces between them to avoid aggravation
>Is there a good rule of thumb for signal
generally, don't use the minimum trace/space unless necessary. the less you push the limits of the manufacturer's process, the better yields and fewer delays you get
KiCAD has a decent PCB calculator. Pic related contains the IPC standard formula for maximum average trace current if you want to math it out manually. try to keep temperature rise not more than 5°C (do not exceed 10°C) on FR-4 for actual average current
when you get into faster or differential signals, impedance starts to become important and you will need closely matched trace widths and constant spacing to avoid perturbing high-speed signals. the PCB calc has your back there too
>power trace widths
generally, avoid running traces to a pad that are as wide as the pad itself (delamination risk increases), or neck them down just before the pad. otherwise, wider is better. board houses would rather ship copper than etch it
now that I understand your design strategy I'll give it a 7/10, if you make a faster board it will probably work nicely